Author Topic: Verilog syntax file  (Read 4260 times)

Heavenlight

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Verilog syntax file
« on: August 13, 2010, 09:56:50 am »
Hello,

I have created and attached here syntax schema for Verilog.

Best regards.

Offline alex

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Re: Verilog syntax file
« Reply #1 on: August 13, 2010, 02:26:10 pm »
Hi Nick,

thanks a lot for new syntax schema and support of HippoEDIT.
If you are not aware, this work cost free HippoEDIT license. Will be send today evening registered to "Nick". If you want another registration name, just send me private message.

About the schema - looks very fine, but I think, we can make it better ;)

First, can you send me some examples you have used that I can test it. I have found some in the internet, bu they are relatively small. To supportbox hippoedit com.

In the schema:
- do you really need to have alternating colors by default on? This display feature is used mostly for flat tables but not source files. And user can always enable it by themselves.
- Is it possible to reuse as much as possible of standard (palette/named) colors instead of explicit ones (#FFAA...)
- I have seen you have tried to do scopes for preprocessor, but with some problems. I will correct it ans send you new schema for review
- Would be good to add labels also (for function definitions and conditional construction for example as if or case etc). If you will send me rich example, I can help here.
- maybe you can provide some minimal set of default templates we can also integrate?

Nevertheless thanks a lot for your work!

Best regards,
Alex.

Heavenlight

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Re: Verilog syntax file
« Reply #2 on: August 16, 2010, 01:51:58 pm »
Hi, Alex,
thanks for the license.

At work on the scheme there were some questions:
1. At attempt to change operators: <Style id = "operator" name = "operator" text = "1" bold = "0" italic = "0" underline = "0" clr = "# 8000FF00" bkclr = "# FFFFFFFF"/>, was gone automatic allocation of opening and closing brackets.
2. What semantic distinction have Operators and Delimiters, i.e. what where it is better to define?
3. On a sign equally "=" the attribute (bold = "1") doesn't operate.
4. Color if only it isn't set directly through # isn't shown in an popup window.
5. Concerning the most color scheme:
 - The given scheme adjusted under itself simply, it is possible to use standard colors certainly;
 - It is desirable to have the complete list of standard colors;
 - Templates I will try to prepare in the near future;
 - The file example has sent on a box.

Best regards,
   Nick.

Offline alex

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Re: Verilog syntax file
« Reply #3 on: August 17, 2010, 11:27:42 pm »
Quote
1. At attempt to change operators: <Style id = "operator" name = "operator" text = "1" bold = "0" italic = "0" underline = "0" clr = "# 8000FF00" bkclr = "# FFFFFFFF"/>, was gone automatic allocation of opening and closing brackets.
Yes. And this is correct. Because you mark style for some reason as text="1", which force HE to treat this style as non-parseable text (as comments) and because, your open close pairs belong to Operators set (in specification node) they also treated as text and processed. Auto Brackets do not work in text style.
In any case you have operator style inherited from defsource_spec.xml. If you just want to change color/style for example, you can extend it.

Quote
2. What semantic distinction have Operators and Delimiters, i.e. what where it is better to define?
I have extended FAQ post with description. Check <SPECIFICATION> part.

Quote
3. On a sign equally "=" the attribute (bold = "1") doesn't operate.
It should work. Is this reproducible with your schema? Can I find an example in verilog file you have sent me? Probably symbol = used twice in spec (as operator also fex) or font you are using does not display bold = well.

Quote
4. Color if only it isn't set directly through # isn't shown in an popup window.
Popup you mean, that display color value for # colors it is Color Informer Tooltip and it has nothing to do with Spec files. it just can recognize web colors and RGB form of colors in text and show it preview. Independently from syntax used. It does not know something about palette colors. But better will be to use Options dialog to set colors: there you will get also preview of palette colors. but be aware, color setting will be written to verilog_user.xml, you need to copy them later to schema as defaults.

Quote
The given scheme adjusted under itself simply, it is possible to use standard colors certainly;
Ok, I will try to find suitable colors from standard. If not, we can use also your explicit colors. But then it can be problem when using over color schemes.

Quote
Templates I will try to prepare in the near future;
Thanks!

Quote
The file example has sent on a box.
I got it. Have not adjust the schema yet, but I will soon.

Best regards,
Alex.


Offline alex

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Re: Verilog syntax file
« Reply #4 on: August 18, 2010, 11:37:59 pm »
Hi Nick,

please verify updated schema. I have added some stuff, something was corrected, something standardized.
With colors I was two lazy to really keep your original highlighted, but just have replaced explicit colors for several from standard defined in all patterns.

If everything will be fine, I will add schema to library on web site.

Best regards,
Alex.

Heavenlight

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Re: Verilog syntax file
« Reply #5 on: August 23, 2010, 08:23:39 am »
Hi Alex.

I have checked updated schema. All is good. However use of such method
Quote
          <Block open="'h ">
            <Close noneof="0-9a-fA-F_xXzZ?"/>
          </Block>
isn't correct as the number of blanks after 'h can be any. Also
Quote
'o1239
is wrong, but worked.

Best regards,
Nick.

Offline alex

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Re: Verilog syntax file
« Reply #6 on: August 23, 2010, 11:18:34 am »
Hi Nick,

thank for checking.

Quote
Quote
          <Block open="'h ">
            <Close noneof="0-9a-fA-F_xXzZ?"/>
          </Block>
isn't correct as the number of blanks after 'h can be any.
because HE currently does not support regular expressions in block conditions it is not possible to configure any number of spaces. But we can add version with two spaces, in addition, than such configuration will cover 95% percent of real usages, I think.

Quote
Quote
'o1239
is wrong, but worked.
Sorry, this is not clear to me... What exactly is wrong, and what is desired result (I have just copied/modified this block from your original schema)?

Also, can you please check Labels. Are they complete/correct?

Best regards,
Alex.

Heavenlight

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Re: Verilog syntax file
« Reply #7 on: August 23, 2010, 12:42:00 pm »
Hi Alex,

Quote
'o1239

<Block open="'o" noneof="0-7_xXzZ?"/>
"9" is not included in noneof group.

Quote
Also, can you please check Labels. Are they complete/correct?
I don't understand what you means in group "Labels", sorry.

Best regards,
Nick.

Offline alex

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Re: Verilog syntax file
« Reply #8 on: August 23, 2010, 01:10:31 pm »
Quote
<Block open="'o" noneof="0-7_xXzZ?"/>
"9" is not included in noneof group.
This was copied from your original schema:
Quote
      <Style id="defdig" name="Defdig" bold="0" italic="0" underline="0" clr="Number" bkclr="#FFFFFFFF">
          <Blocks>
              <Block open="'b" noneof="0-1_xXzZ?"/>
              <Block open="'d" noneof="0-9_xXzZ?"/>
              <Block open="'o" noneof="0-7_xXzZ?"/>
              <Block open="'h" noneof="0-9a-fA-F_xXzZ?"/>
          </Blocks>
      </Style>
But Ok, I will correct it.

Quote
I don't understand what you means in group "Labels", sorry.
What I mean is this part:
Quote
    <LABELS>
      <Label group="Module" match="module\s+(\w+)\s*(\([^)]*\))\s*;" name="\1" descr="\1 \2" scope="1" image="18"/>
      <Label group="Function" match="function\s*(\[\d:\d\])\s*(\w+)\s*;" name="\2" descr="\1 \2" scope="1" image="11"/>
      <Label group="" match="(if|for)\s*\(((?:[^\(\)]|\\r|\\n|\((?-1)\))*+)\)\s+begin" name="\1" descr="\1 (\2)" scope="1" image="13" navigation="false"/>
    </LABELS>

It describes so called labels, which can mark some areas of text with description, based on parsing regexp. For example two first used to search for module and function definitions in verilog files and connect them to scope. You can see labels list in navigation bar. This is something like Function list in other editors.
I have added only definitions for module and functions and also for if for construction. If something missing you can add it and than I will update spec with them.

Heavenlight

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Re: Verilog syntax file
« Reply #9 on: August 23, 2010, 02:44:04 pm »
I mean, when you write 'o1239, it should not be highlighted, because "9" is not included in noneof group (and its right).

Offline alex

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Re: Verilog syntax file
« Reply #10 on: August 23, 2010, 08:37:45 pm »
that is funny, of course, but it works :)
Just in example you have suggested 'o1239, there are two areas highlighted:
first 'o123, based on block condition:
Quote
<Block open="'h ">
   <Close noneof="0-9a-fA-F_xXzZ?"/>
</Block>
and second based on generic number highlighting, based on specification for language:
Quote
<Words init="A-Za-z_?0-9">0-9A-Za-z_?</Words>

you can find this out, if you will hover over the text with mouse and keep Ctrl+Shift+Alt pressed.

Because normally 9 can go after any character, there is no way to handle this situation correctly now, so let us leave it like it is.

If there uis no other comments, I think, Verilog schema is fine now and I will place it to library.

Best regards,
Alex

 

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